This invention relates to electrical idle exit detection for clock-data recovery circuitry in a high-speed serial interface of a programmable integrated circuit device such as a programmable logic device.
As it becomes more important to minimize power consumption in programmable logic devices with embedded high-speed serial interfaces, it is desirable to use power-saving modes provided by the serial protocols supported by the devices to the fullest extent possible. One such mode is the PCI Express L0 Standby (L0s) low-power mode in which a link is placed in electrical idle when a lull in packet traffic is anticipated. This mode is intended for frequent usage and hence necessitates robust low-latency electrical idle entry and exit mechanisms in order to meet the performance demands of high-speed applications. Electrical idle entry and exit have heretofore been detected by an analog “signal detection” approach in which the signal detected by the receiver is compared to a protocol-defined voltage threshold.
This approach has been shown to be increasingly unreliable, especially in the context of emerging protocols such as PCI Express Gen 2 in which the receiver sensitivity at 5 Gb/s is 120 mV and the idle detection threshold is 175 mV. Specifications such as PCI Express Gen 2 have therefore been enhanced to include electrical idle entry inference mechanisms that are implemented in the digital domain and reduce or eliminate dependency on the “signal detection” mechanism. These idle entry mechanisms generally are easily implemented.
However, the corresponding mechanisms specified to infer electrical idle exit, such as the detection of a recurring low frequency pattern of successive K28.7 symbols prior to LOs exit, are designed to be implemented in the analog domain and necessitate a bit lock time of less than 32 ns, which may not be feasible for the vast majority of clock data recovery (CDR) implementations. Nevertheless, whatever mechanism is used must meet the low-power mode exit latency specified by the relevant protocol. Under PCI Express, the low-power mode exit latency should not exceed 4 μs for PCI Express Gen 1, or 2 μs for PCI Express Gen 2. And in practice, most current applications demand low-power mode exit latencies about 1/16 of those maxima, or as low as about 125 ns.
It would be desirable to be able to provide a CDR control architecture for low-latency electrical idle exit detection which is applicable to all CDR implementations, and which is not based on the unreliable “signal detection” mechanism described earlier.